1. Field of the Invention
The present invention generally relates to clamp circuits and, more particularly, to a fast, low output impedance, low-power clamp circuit.
2. Discussion of the Related Art
Analog multiplexer circuits are used for distributing multiple analog signals to a single output, one at a time. As shown in FIG. 1, an analog multiplexer 100 includes N open-loop buffers 102.sub.i. Each buffer 102.sub.i is a single input, single output, unity gain amplifier that either is enabled (to pass the input to the output) or disabled (to prevent the input from passing to the output). Each input lead 104i carries one analog signal. An N:1 analog multiplexer can be constructed by connecting each input of buffer 102.sub.i to a respective input lead 104i. The outputs of the N open-loop buffers 102.sub.i are connected together as a shared output lead 106. In operation, only one of the buffers 102.sub.i at a time is enabled and the corresponding input 104i connected thereto controls a voltage potential of the shared output lead 106, while the other buffers 102.sub.i remain disabled. Ideally, it is desired that the one enabled buffer would have a gain A of one (1) while the disabled buffers each have a gain of zero (0).
A conventional complementary emitter follower 200, as shown in FIG. 2, can be modified to serve as a switchable open-loop buffer 102.sub.i in multiplexer 100. Complementary emitter follower 200 includes PNP transistors Q11, Q22, NPN transistors Q12, Q21, current sources IP1, IN1, first supply line 201, second supply line 203, input lead 104i and output lead 202.
Complementary emitter follower 200 receives an analog input signal voltage VI at an input lead 104i and outputs an analog output signal voltage VO on output lead 202 substantially equal to the input signal voltage VI.
As shown in FIG. 2, the base of transistor Q11 is coupled to input lead 104i and the collector is coupled to the second supply line 203. The base of transistor Q21 also is coupled to input lead 104i and the collector is coupled to the first supply line 201. Current source IP1 is coupled between the first supply line 201 and the emitter of transistor Q11. The base of NPN transistor Q12 is coupled to the emitter of PNP transistor Q11, the collector is connected to the first supply line 201 and the emitter is connected to output lead 202. The emitter of PNP transistor Q22 is coupled to the output terminal 202 and the collector is coupled to the second supply line 203. Current source IN1 is coupled between the second supply line 203 and the emitter of the NPN transistor Q21. The first supply line 201 receives supply voltage V.sub.CC and the second supply line receives supply voltage V.sub.EE.
To enable the follower 200, current sources IP1 and IN1 are turned on, each providing an emitter current to transistors Q11 and Q21, respectively. These transistors, in turn, forward bias transistors Q12 and Q22, respectively, which completes the complementary signal path from the input lead 104i of the follower 200, receiving input signal voltage VI, to the output lead 202 providing output signal voltage VO.
To disable the follower 200, the current sources IP1 and IN1 are turned off, which eliminates the emitter currents of transistors Q11 and Q21. This leaves the collector currents of all four devices, i.e., transistors Q11, Q12, Q21 and Q22, at almost zero and the base nodes of transistors Q12 and Q22 as DC open circuits.
In this off state, i.e., disabled state, the input lead 104i and output lead 202 of the follower 200 are isolated from one another by two parallel paths P.sub.1, P.sub.2 ; the first path P, including transistors Q11 and Q12 and the second path P.sub.2 including transistors Q21 and Q22. Each of these paths P.sub.1, P.sub.2 includes back-to-back, zero-biased emitter-base junctions. Using first path P.sub.1 as an example, if the transistors all have equal junction capacitances and the external source impedance is low, then the small-signal off transmission value A,, i.e., the reciprocal of the isolation value, of first path P.sub.1 is characterized by a single time constant .tau. and is given by: ##EQU1## where s=j.omega. is the Laplace transform variable, R.sub.L is the load resistance, and C.sub.je11 and C.sub.je12 are the emitter-base capacitances of transistors Q11 and Q12, respectively. In other words, the gain A.sub.1 is proportional to frequency and it is desirable, therefore, to make .tau. small.
In many applications, however, the isolation afforded by simply opening the bases of the output transistors Q12 and Q22, as in FIG. 2, is inadequate. The "off-isolation" of the follower 200 can be improved by clamping each of the bases of the output transistors Q12 and Q22 with a low impedance source when the follower 200 is disabled.
As shown in FIG. 3, a conventional complementary emitter follower 200' is provided with conventional base clamp circuits 302, 304. The clamped complementary emitter follower 200' has the same structure as the follower 200 shown in FIG. 2, except for the addition of the two clamp circuits, 302, 304. All similarly labeled elements function as described above with regard to FIG. 2.
Inserted into the first path P.sub.1 of the clamped follower 200', clamp circuit 302 includes clamping NPN transistor Q10, current source IP0 and first bias supply lead 303. Clamp circuit 304 inserted into the second path P2, includes clamping PNP transistor Q20, current source IN0 and second bias supply lead 305. The collector of clamping NPN transistor Q10 is coupled to the first supply line 201 and its emitter is coupled to the base of the NPN transistor Q12. The base of clamping transistor Q10 is coupled to the first bias supply lead 303. The current source IP0 is coupled between a supply lead V.sub.EE and the emitter of clamp transistor Q10. Node A represents a junction of the emitter of clamp transistor Q10, i.e., the output of clamp circuit 302, and the base of NPN transistor Q12. The first bias supply lead 303 receives bias voltage VCP.
In clamp circuit 304, the collector of clamping PNP transistor Q20 is coupled to the second supply line 203, its base is coupled to the second bias supply lead 305 and its emitter is coupled to the base of the PNP transistor Q22. The second current source IN0 is coupled between a supply lead V.sub.CC and the emitter of transistor Q20. Node A' represents a junction of the emitter of the clamping transistor Q20, i.e., the output of the clamp circuit 304, and the base of the PNP transistor Q22. The second bias supply lead 305 receives bias voltage VCN.
When the clamped follower 200' is enabled, as per the description above with regard to follower 200, current sources IP0 and IN0 are turned off. Bias voltages VCP and VCN, respectively, are set to values which bias transistors Q10 and Q20 in cutoff. As a result, the operation of the clamped follower 200' is similar to that of the unclamped follower 200 shown in FIG. 2. In other words, the output signal voltage VO at output lead 202 follows the input signal voltage VI at input lead 104i.
When the clamped follower 200' is disabled, current sources IP1 and IN1 are turned off and current sources IP0 and IN0 are turned on. Transistors Q10 and Q20 are, therefore, forward biased which turns off transistors Q12 and Q22. The "off isolation" of the clamped follower 200' is equivalent to that of two open T-switches in parallel; the first T-switch consisting of transistors Q11, Q10 and Q12 and the second T-switch consisting of transistors Q21, Q20 and Q22. As can be seen, each T-switch consists of back-to-back reverse-biased emitter-base junctions, a common node of each of which is driven by a low impedance source.
A small-signal model for the first T-switch, i.e., first path P, and clamp circuit 302, of the emitter follower 200' is shown in FIG. 4. The small-signal model includes two capacitors C.sub.je11, C.sub.je12 and two resistors R.sub.CLAMP, R.sub.L. In the model, as per the discussion of Equation 2 above, the capacitors C.sub.je11 and C.sub.je12 represent the emitter-base capacitances of transistors Q11 and Q12, respectively. The resistance R.sub.CLAMP represents the impedance of the clamp circuit 302 and resistance R.sub.L represents the load resistance. In the small-signal model, the goal is to have R.sub.CLAMP be as small as possible so as to get a best possible "off isolation."
Representing the current from each of current sources IP0 and IN0 as I0 and assuming that the transistors all have equal junction capacitances, the approximate low-frequency transmission, or gain, A.sub.2 of the first path P.sub.1 of the clamped follower 200' is given by a ratio of V.sub.0 to V.sub.i : ##EQU2## EQU .tau..sub.1 R.sub.CLAMP C.sub.je11 ( 4) EQU .tau..sub.2 =R.sub.L C.sub.je12 ( 5)
where R.sub.CLAMP is the output resistance of the clamp circuit and R.sub.L is the load resistance and, as above, s=j.omega.. In Equation 3, the gain A.sub.2 varies as the square of the frequency.
The output resistance R.sub.CLAMP is given as follows: ##EQU3## where k is Boltzmann's constant, T is the absolute temperature in degrees Kelvin, q is the electron charge, and I.sub.o is the quiescent output current. At room temperature, i.e., 27.degree. C. (300.degree. K.), the value of (kT/q) is approximately 25.85 millivolts.
As can be seen, if the transistors Q10 and Q20 have low base resistances and are driven by low impedance sources, then the isolation of the clamped complementary emitter follower 200' is proportional to the current I0. Since the currents provided by current sources IP0 and IN0 are also the slew currents for the bases of transistors Q12 and Q22, respectively, the switching time of the follower 200' is inversely proportional to current I0. Therefore, to provide faster switching time, more current is required. However, this means larger power consumption for the device since the current will be necessary whether the follower 200' is disabled or enabled. Thus, there is a conflict between the need for faster switching speed versus the requirements of lower power consumption and the compromises between them which must be made.
It therefore is a general object of the present invention to provide a clamp circuit which provides relatively high speed switching and also has low power consumption.